1. Field of the Invention
The present invention relates to a multi-chip package and manufacturing method thereof. More particularly, the present invention relates to a high electrical performance multi-chip package that can be manufactured with fewer processing steps.
2. Description of the Related Art
In this information-centered society, everyone is shopping around for high speed, high quality, and multifunctional products. As far as aesthetic appearance is concerned, most products are designed to be slim, compact, light and easy to use. In order to achieve the above goals, most manufacturers will incorporate system design concepts into their products so that a single chip can have a variety of functions. Ultimately, the total number of chips inside each electrical product and the circuit volume can be reduced. Furthermore, to reduce the size and weight of each chip package, a few packaging methods has been developed. The chip packaging techniques commonly deployed include multi-chip module (MCM), chip-scale package (CSP) and stacked multi-chip package.
FIG. 1 is a schematic cross-sectional view of a conventional multi-chip package. As shown in FIG. 1, the multi-chip package 100 includes three chips 110, 120, 130, a plurality of insulation layers 140, 142, 144, 146, three metallic layers 150, 152, 154 and a plurality of solder balls 160. Each of the chips 110, 120, 130 has a plurality of chip bonding pads 114, 124, 134 located on their respective active surfaces 112, 122 and 132.
To manufacture the multi-chip package 100, the backside 126 of the chip 120 is attached to the active surface 112 of the chip 110 using an adhesive material 170. The insulation layer 140 is formed on the active surface 112 of the chip 110 to enclose the chip 120. Thereafter, the insulation layer 140 is patterned to form a plurality of via holes 141a and 141b that expose the bonding pads 114 and 124. A metallic layer 150 is formed over the insulation layer 140 and fills the via holes 141a and 141b. Photolithographic and etching processes are carried out to pattern the metallic layer 150 and then another insulation layer 142 is formed over the insulation layer 140 and the metallic layer 150.
Afterwards, the backside 136 of the chip 130 is attached to the insulation layer 142 using an adhesive material 172. Another insulation layer 144 is formed over the insulation layer 142 so that the chip 130 is entirely enclosed. The insulation layers 144 and 142 are patterned to form a plurality of via holes 144a and 144b that exposes a portion of the metallic layer 150 and the bonding pads 134. Thereafter, a metallic layer 152 is formed over the insulation layer 144 such that the via holes 144a and 144b are filled with the metallic layer 152. Photolithographic and etching processes are carried out to pattern the metallic layer 152 and then an insulation layer 146 is formed over the insulation layer 144 and the metallic layer 152. The insulation layer 146 is patterned to form a plurality of openings 147 that exposes the metallic layer 152. Another metallic layer 154 is formed over the insulation layer 146 such that the openings 147 are filled with the metallic layer 154. Thereafter, photolithographic and etching processes are again used to pattern the metallic layer 154. Finally, a plurality of solder balls 160 are attached to the metallic layer 154 so that the multi-chip package 100 can connect electrically with an external circuit (not shown) via the solder balls 160.
In the aforementioned multi-chip fabricating process, after stacking the chip 120 on the chip 110, a pair of insulation layers 140, 142 and a metallic layer 150 are formed to electrically connect the chips 110 and 120. Furthermore, after attaching the chip 130 to the insulation layer 142, another pair of insulation layers 144, 146 and a metallic layer 152 are formed to electrically connect the chips 110, 120 and 130. In other words, at least an insulation layer and a metallic layer must be formed whenever an additional chip is attached to the multi-chip package. Moreover, the via holes 141a, 144a that pass through various insulation layers has a depth approximately equal to the thickness of a chip. Hence, the manufacturing process is time-consuming and highly inefficient.
In addition, the chips 110, 120130 are interconnected through the metallic layers 150 and 152 and hence the average length of electrical pathways connecting the chips 110, 120, 130 are longer. Consequently, the multi-chip package will have a somewhat larger distortion in internal signal transmission.